Time：November 1, Wednesday, 15:00-16:00, 2023
Venue：#Tencent Meeting：198-332-257
Abstract:
Image compression technology is crucial for alleviating the burden of image transmission and storage. Traditional image compression standards have been developed for over 30 years. On the other hand, with the rapid advancement of neural network technology, Learning-based Image Compression (LIC) has demonstrated exceptional capabilities in terms of compression ratio and image quality when reconstructing images. The latest LIC outperforms the most recent traditional coding standard, VVC, in terms of intra-prediction. To accelerate encoding speed, most LIC frameworks operate on GPUs using floating-point algorithms. However, if encoding and decoding are performed on different platforms, mismatches in floating-point computations on various hardware platforms can lead to decoding errors. Hence, there is a strong need for LIC with fixed-point arithmetic.
This report presents an FPGA design for LIC with 8-bit fixed-point quantization. Unlike existing FPGA accelerators, we propose a fine-grained pipeline architecture to achieve high DSP efficiency. Lastly, we introduce a CPU-FPGA heterogeneous system, with arithmetic encoding allocated on the CPU and neural networks allocated on the FPGA. A demonstration will also be provided to showcase real-time encoding systems.
Biography:Professor Heming Sun obtained his Bachelor's degree in Electronic Engineering from Shanghai Jiao Tong University in 2011. In 2012 and 2014, he pursued dual-degree programs and received his Master's degrees from Waseda University and Shanghai Jiao Tong University, respectively. In 2017, he earned his Ph.D. in Informatics from Waseda University. From 2017 to 2018, he served as a researcher at the NEC Central Research Laboratory. From 2018 to 2023, he worked as an Assistant Professor at Waseda University. Currently, he holds the position of Associate Professor at Yokohama National University. Between 2019 and 2023, he was selected as a researcher by the Japan Science and Technology Agency (JST) PRESTO program. His research interests lie in the algorithms and VLSI architectures for image/video processing and neural networks. He has received numerous awards, including the IEEE Computer Society Japan Chapter Young Author Award, VICIP Best Paper Award, VICIP Best Reviewer Award, PCS Best Paper Finalist, and the ISSCC Takuo Sugano Outstanding Far East Paper Award, among others. He is an active member of the IEEE CAS VSPC TC and serves as an Associate Editor for IEEE Transactions on Circuits and Systems for Video Technology and a Guest Editor for IEEE Circuits and Systems Emerging and Selected Topics Journal. He has delivered three tutorial lectures on learning-based image/video compression at IEEE ISCAS, IEEE/CVF WACV, and IEEE/CVF ICCV.